The industry continues to add more computational power to chips through increased levels of parallelism — the buzzword used to be “multi-core” (now being used for dual- and quad-core CPUs), now it is moving to “many-core” (16-, 32- or even 100-cores per chip).
Intel’s Larrabee architecture looks to be the first candidate — available sometime in 2010 — and should provide up to 32-cores per chip. It’s initial versions will be targeted at discrete graphics, but it is expected to migrate into the HPC market.
Jayesh Patel from Intel will be joining us on Wednesday, November 4th (4-5pm, Schiciano Auditorium, FCIEMAS) to talk about using SSE instructions to accelerate your application. He will also cover some of the upcoming new features of the next-generation SSE — called AVX (Advanced Vector Extensions). The Intel compilers also provide OpenMP and other auto-parallelization features, and Intel further provides optimized libraries for a variety of “standard” mathematical functions (Intel Performance Primitives and the Math Kernel Library). The talk will focus on practical advice and how you can leverage Intel’s software stack in your own applications.
Please join us in the Schiciano Auditorium (FCIEMAS Building), 4-5pm on Wednesday, November 4th.
The SCSC will be offering several seminars on virtualization tools and technologies over the last two weeks of October:
For more information, see the SCSC Wiki.
Some GPU-computing news:
We will be trying out the new Duke blog service over the next few months to post information of relevance to the scientific-, high-performance-, and research-computing communities. Some of the articles will be re-posts from other HPC blogs, some will be authored by SCSC staff, and maybe some will be authored by YOU (let us know if you have a story to post).